An embodiment of this disclosure relates to a semiconductor memory device and, more particularly, to a semiconductor memory device including stacked word lines.
In semiconductor memory devices, as the size of a memory cell is gradually decreased to increase the integration degree, the manufacturing process becomes more difficult. To address such features, a three-dimensional (3-D) semiconductor memory device having a Pipe-shaped Bit Cost Scalable (hereinafter referred to as a P-BiCS) structure formed by stacking memory cells has been developed. The 3-D semiconductor memory device having a P-BiCS structure is described in detail below.
FIG. 1 is a circuit diagram illustrating a memory array included in a conventional semiconductor memory device having a P-BiCS structure.
Referring to FIG. 1, each of memory blocks BLOCKa and BLOCKb includes a plurality of memory strings ST. In the P-BiCS structure, each of the memory strings ST includes a first memory string vertically coupled between a common source line CSL and the pipe transistor of a substrate and a second memory string vertically coupled between a bit line BL and the pipe transistor of the substrate. The first memory string includes a source select transistor SST and memory cells C0 to C7. The source select transistor SST is controlled by a voltage supplied to a source select line SSLa1, and the memory cells C0 to C7 are controlled by a voltage supplied to stacked word lines WLa0 to WLa7. The second memory string includes a drain select transistor DST and memory cells C8 to C15. The drain select transistor DST is controlled by a voltage supplied to a drain select line DSLa1, and memory cells C8 to C15 are controlled by a voltage supplied to stacked word lines WLa8 to WLa15.
In the memory string of the P-BiCS structure, a pipe transistor PT coupled between the pair of memory cells C7 and C8 placed in the middle of the first and the second memory strings functions to electrically couple the channel layers of the first memory strings and the channel layers of the second memory strings which are included in the memory block BLOCKa when the memory block BLOCKa is selected.
Meanwhile, in a memory block having a two-dimensional (2-D) structure, a memory string is coupled to each bit line, and the drain select transistors of the memory block are controlled by a single drain select line at the same time. In the memory block BLOCKa of the 3-D structure, the plurality of memory strings ST is coupled to each bit line BL in common. The number of memory strings ST coupled to one bit line BL in common and controlled by the same word lines in the same memory block BLOCKa may be changed according to different design needs. FIG. 1 shows a 4-string structure in which four memory strings ST are coupled to one bit line BL in common. Since the plurality of memory strings ST is coupled in parallel to the bit line BL, the drain select transistors DST are independently controlled by respective select voltages supplied to the drain select lines DSLa1 to DSLa4 in order to selectively couple the bit line BL and the memory strings ST.
In the memory block BLOCKa, the memory cells C0 to C7 of the first memory string and the memory cells C8 to C15 of the second memory string, each of which are vertically coupled, are controlled by operating voltages supplied to the stacked word lines WLa0 to WLa7 and the stacked word lines WLa8 to WLa15, respectively. The word lines WLa0 to WLa15 are classified for each memory block. That is, the memory cells of the memory block BLOCKa are operated by voltages supplied to the word lines WLa0 to WLa15, and the memory cells of the memory block BLOCKb are operated by voltages supplied to the word lines WLb0 to WLb15. In other words, when the memory block BLOCKa is selected, operating voltages are supplied to the word lines WLa0 to WLa15, and thus the memory cells of the memory block BLOCKa are operated. When the memory block BLOCKb is selected, operating voltages are supplied to the word lines WLb0 to WLb15, and thus the memory cells of the memory block BLOCKb are operated.
In order to supply the operating voltages to the memory string ST having the above structure, at least 21 lines, including 16 lines coupled to the word lines WLa0 to WLa15, 4 lines coupled to the drain select lines DSLa1 to DSLa4, and 1 line coupled to control the pipe transistor PT, are used for each memory block.
Meanwhile, in order to further increase the integration degree, a larger number of memory cells are to be disposed in the same area. In the P-BiCS structure, a larger number of memory cells are vertically coupled. In this case, the number of stacked word lines is increased, and thus, the number of lines for transferring operating voltage to a memory block increases. If the number of lines is increased, however, it becomes difficult to dispose lines since the size of peripheral circuits (for example, a voltage generator and a row decoder) for supplying the operating voltages to the lines is increased and an internal structure design is to be changed to accommodate such a change in the size of peripheral circuits. That is, in order to increase the integration degree, a design of internal structure is significantly changed.